The present invention relates to semiconductor switching devices known as power MOS or MOSFET devices.
Power MOSFETs are voltage-controlled devices which require only a small input current for switching. In comparison to a conventional bipolar transistor device, switching speed is higher, and therefore switching times are faster. As such, these devices are finding increasing applications in low-power, high-frequency converters.
Industry currently provides two general types of MOSFETs including a depletion mode and an enhancement mode device. These two types of MOSFETs may be formed by either n-channel or p-channel technology, or the like. However, all MOSFETs characteristically possess three terminals including a gate, drain, and source. The gate is always isolated from a channel region by a thin oxide layer (typically between 200 to 1200 angstroms). A thinner oxide layer usually requires less voltage to turn-on the device.
As for gate construction, commercial devices were first developed with a metal gate (i.e., aluminum). From a circuit perspective, it suffers severe drawbacks. In particular, the metal gated device requires a higher threshold voltage to turn-on the device than other MOS technologies, thereby resulting in a higher power requirement.
Another drawback with the metal gated device is its operating speed. Operating speed is a function of time required to turn-on and/or turn-off the device. Its effect over the entire MOS circuit is termed access time. The metal gated device inherently produces a structure where the metal gated region overlaps the adjacent source and/or drain regions. This gate overlap gives rise to a parasitic capacitance, thereby impairing device access time, operating speed, and device turn-on and/or turn-off.
Therefore, polysilicon gated technology was introduced to reduce the problems inherent with the metal gated device. The polysilicon gated devices provide lower threshold voltages and faster switching characteristics than their metal gated predecessors. Parasitic capacitance also decreases through a unique fabrication sequence which reduces the gate overlap. This unique fabrication sequence produces a self-aligned gate by forming the gate region before the source and drain diffusions. Currently, industry provides state-of-art power MOS devices with the polysilicon gated material.
However, even state-of-art polysilicon gated devices inherently possess severe limitations with the faster switching characteristics (typically 1 MHz to 900 MHz) required by today's technologies. The polysilicon gate typically has a resistance of about 20 ohms/SQ and includes portions overlying a channel region and field region. Each gate also has significant capacitance between it and its corresponding MOS source and/or drain regions. Both the resistance (R) and capacitance (C) are "parasitic" to the active circuit of the device. Since a polysilicon gated integrated circuit relies predominately upon the polysilicon gate layer to provide the interconnections between the gates within each active device, the parasitic factors combine producing a gate bus having a relatively high RC per unit length of gate. This high RC value causes significant delays during device turn-on and/or turn-off. Resistance R also contributes to energy loss via heat dissipation. During high frequency switching (typically 1 MHz to 900 MHz), the combination of these losses lead to excessive heating, thereby limiting the useful frequency range of the device.